In a typical computer architecture, parallel processors can enforce strict memory models of in-order execution of stores and loads. However, memory models are becoming weaker as systems with large numbers of memory-coherent processors are becoming common. To prevent a race condition and guarantee that a desired store to memory by one processor in a system is visible to other processors in the system, memory ordering operations such as barrier instructions must be used by a programmer and/or a compiler and/or some other form of code generator. It is easy for programmers and compilers to accidentally omit these memory ordering operations even though a race condition is not desired. This can lead to unpredictable and incorrect program execution. Therefore, there exists a need for a better way to determine whether a desired memory ordering operation has been omitted.